Hands-on introduction to the IceStorm open source FPGA toolchain
Description
The open source FPGA toolchain comprising of Yosys and nextpnr has been improving over the last 3 years and is now capable of synthesizing soft cores that can run Linux. The tools are not only lightweight, but also fast, opening up new avenues of exploration such as synthesising bitstreams on demand.
This workshop aims to give a good general overview of the state of the tools and how to use them. Some time will be allowed for experimentation with the tools and participant’s own designs.
We introduce the icebreaker - a new FPGA development board with the low power iCE40 FPGA, designed for teaching and experimentation. After installing and getting to grips with the toolchain, everyone will deploy a simple system-on-chip based on the formally verified picorv32 RISC-V softcore onto it.
We will also demonstrate some projects based on the tools:
- Glasgow: open source digital exploration tool that synthesises new bitstreams on demand
- VexRiscv RISC-V system-on-chip running Linux, built using the open source Python-based LiteX SoC generator, and capable of generating bitstreams itself
In this short workshop, participants will:
- Get an overview of the current open source tools
- Understand how the toolchain works
- See which FPGAs are currently supported, and which are coming in the near future
- Use the toolchain to synthesise their own designs
- Use the IceBreaker development board to run their designs, including a simple low power soft RISC-V SoC
Requirements
- Some experience of a HDL, ideally Verilog
- A laptop with Linux or macOS, if you want to have the tools installed on your own machine
- icebreaker FPGA boards will be provided, and may be taken home at the end
Outline
- Introduction to the open source flow
- Hands on with the tools: part 1 - installation, getting started, blinking an LED
- Demo - Glasgow (open source JTAG tool taking advantage of a deeply embedded FPGA toolchain)
- Hands on with the tools: part 2 - deploying the picorv32 RISC-V softcore to the icebreaker
- Demo - creating new bitstreams from within a softcore running Linux
Organiser - David Shah
David is an engineer at Symbiotic EDA, working on open source design and verification tools including Yosys and nextpnr. He is the developer of the end-to-end open source “Trellis” flow for ECP5 FPGAs.
Questions? Email david@symbioticeda.com